`ifndef __COMMON_SVH__
`define __COMMON_SVH__
`default_nettype none

`define PERF_EVENT(name,cond) `PERF_EVENT_MULT(name,cond,1) //perf_event #(`"name`") inst_perf_event``name ( .inc(cond), .*)
`define PERF_EVENT_MULT(name,cond,width) perf_event #(`"name`",width) inst_perf_event``name ( .inc(cond), .*)

`define ITCM_IMAGE "./itcm_image.txt"
`define DTCM_IMAGE "./dtcm_image.txt"
`define DTCM_SIZE 64*1024

`define WORD_BITS 64
`define RESET_PC 64'h8000_0000
`define IRAM_WIDTH 2 // The instruction ram width means ram can supply IRAM_WIDTH instructions per cycle.
`define IRAM_AW $clog2(`IRAM_WIDTH)
`define IRAM_SIZE 64*1024

`define HAS_IBUF
`define IBUF_SIZE 32
`define IBUF_AW $clog2(`IBUF_SIZE)

//BPU Config
`define BTB_SIZE 128
`define RAS_SIZE 32
`define BTB_AW $clog2(`BTB_SIZE)
`define RAS_AW $clog2(`RAS_SIZE)

`define ARF_SIZE 32 // arch reg file size
`define ARF_AW $clog2(`ARF_SIZE)

`define PRF_SIZE 92 // phy reg file size
`define PRF_AW $clog2(`PRF_SIZE)


`define ROB_SIZE 92
`define ROB_AW $clog2(`ROB_SIZE)

`define GC_NUM 128 // global checkpoint num

`define ALU_NUM 2
`define BRU_NUM 1
`define LSU_NUM 1
`define MDU_NUM 1
`define MISC_NUM 1

`define ALU_IQ_SIZE 16
`define BRU_IQ_SIZE 8
`define LSU_IQ_SIZE 8
`define MDU_IQ_SIZE 8
`define MISC_IQ_SIZE 4

`define STQ_SIZE 8

`define DEBUG

`include "bundle.svh"

`endif  //__COMMON_SVH__
